The present invention relates to an arithmetic logic unit (ALU) for doing floating-point calculations on numbers having a fraction and an exponent.
In an ALU for floating-point arithmetic, any operation can be broken down to an addition or substraction, with the subtraction being an addition after one of the numbers has been complemented. Six basic operations are performed on the operands in series as set forth below:
(a) exponent compare; PA0 (b) pre-alignment (right shifting of the fraction of the number with the smaller exponent); PA0 (c) complementation of one of the fractions if doing subtraction; PA0 (d) addition of both fractions; PA0 (e) post-normalization (left shifting of the result fraction until all leading zeroes are removed); and PA0 (f) updating the result exponent by the amount the fraction was shifted. PA0 (a) exponent compare; PA0 (b) pre-alignment; PA0 (c) complementation of shifted fraction if doing subtraction; and PA0 (d) addition of the two fractions. PA0 (a) complementation of fractions if doing subtraction; PA0 (b) addition of the two fractions; PA0 (c) post-normalization; and PA0 (d) exponent updated by shift amount.
The first step, (a) exponent compare, is used to determine which of the other steps are needed. In particular, step (b), pre-alignment, is not needed if the exponents are close. Thus, the operand is simply passed through the pre-alignment circuitry without shifting. The operands pass through stages for all of these operations in series.